mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 931

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 38 Serial Peripheral Interface (SPI)
RESET
Configure DMA Controller
for SPI transmission
Configure SPI before Transmission
Set SPE=1 to start transmission in
master mode or enable SPI for
transmission in slave mode
Read SPI status register
Write the first byte to SPI data register
via CPU
Set TXDMAE to enable Transmit by
DMA
Wait for interrupt(s) of DMA Controller
indicating end of SPI transmission
Figure 38-37. Recommended startup of SPI transmit by DMA
38.4.5.2 Receive by DMA
Receive by DMA is supported only when RXDMAE is set. A receive DMA request is
asserted when both SPE and SPRF are set. Then the on-chip DMA controller detects this
request and transfers data from the SPI data register into memory. After that, RX DMA
DONE is asserted to clear SPRF automatically. This process repeats until all data to be
received (the number is decided by configuration register[s] of the DMA controller) is
received or no receive DMA request is generated again because the SPI transmission is
finished.
When the FIFO feature is supported: In FIFO mode (FIFOMODE=1) and when a data
length of 8 bits is selected (SPIMODE=0), the DMA transfer for one receive DMA
request can read more than 1 byte (up to 8 bytes) from the SPI data register because the
RX FIFO is full with 8 bytes. In FIFO mode (FIFOMODE=1) and when a data length of
16 bits is selected (SPIMODE=1), the DMA transfer for one receive DMA request can
read more than 1 word (up to 4 words) from the DH:DL registers because the RX FIFO is
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
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