mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1264

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Descriptions
1264
WRITE_CSR2_BYTE
READ_DREG
WRITE_DREG
WDEBUG instruction
DRc: 0x02 (CSR2)
R
W
Power-on
Reset
Other
Reset
R
W
Reset
PSTBP
Field
31
30
31
PST
BP
1
0
15
30
0
1
0
14
Reference method
PST Buffer Stop
Signals if a PST buffer stop condition has been reached.
0
1
Reserved. Must write 0.
Description
29
COP
HR
0
u
13
Undefined and Unaffected
Table 50-11. CSR2 Access Summary (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
IOP
HR
0
u
12
PSTBWA
Table 50-12. CSR2 Field Descriptions
Stop condition has not been reached
Stop condition has been reached
27
IADH
R
0
u
11
Table continues on the next page...
26
0
0
0
10
Preliminary
25
BFH
BR
0
u
9
24
0
BDF
R
0
0
8
Writes bits 31–24 from the BDM interface. Available in all
modes.
Reads bits 31–0 from the BDM interface. Classified as a non-
intrusive BDM command.
Writes bits 23–0 from the BDM interface. Classified as a non-
intrusive BDM command.
Writes bits 23–0 during execution of the core WDEBUG
instruction. This instruction is a privileged supervisor-mode
instruction.
23
0
0
7
0
0
PST
BH
22
0
0
6
0
PSTBST
21
0
0
5
0
0
Details
20
0
0
0
4
0
PSTBRM
Freescale Semiconductor, Inc.
Access: Supervisor read-only
19
0
0
3
0
18
0
0
2
0
D1HRL
BDM read/write
PSTBSS
17
1
1
1
0
16
1
1
0
0