mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 337

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mcf51jf128

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mcf51jf128
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Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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15.2 External Signal Description
The CF1_INTC module does not include any external interfaces.
15.3 Interrupt Request Level and Priority Assignments
The CF1_INTC module implements a sparsely populated 7 × 9 matrix of levels (7) and
priorities within each level (9).
Refer to the Chip Configuration information for assignment details for the device.
15.4
The CF1_INTC module provides a 64-byte programming model mapped to the upper
region of the 16 MB address space. All the register names are prefixed with INTC_ as an
abbreviation for the full module name.
In the programming model, attempted references to undefined (reserved) addresses or
with a non-supported access type (for example, a write to a read-only register) generate a
bus error termination.
The programming model follows the definition from previous ColdFire interrupt
controllers. This compatibility accounts for the various memory holes in this module
memory map.
The CF1_INTC module is referred to as CF1_INTC_BASE throughout the chapter and
occupies the upper 64 bytes of the peripheral space.
Freescale Semiconductor, Inc.
Memory Map and Registers
For remapped and forced interrupts, the interrupt source
number entry indicates the register or register field that enables
the corresponding interrupt.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Note
Chapter 15 Interrupt Controller (INTC)
337

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