mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 333

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

All ColdFire processors support a 1024-byte vector table aligned on any 1 MB address
boundary. For the V1 ColdFire core, the only practical locations for the vector table are
based at 0x(00)00_0000 in the flash or 0x(00)80_0000 in the RAM. The table contains
256 exception vectors; the first 64 are reserved for internal processor exceptions, and the
remaining 192 are device-specific interrupt vectors. The IRQ assignment table is partially
populated depending on the exact set of peripherals for the given device.
Freescale Semiconductor, Inc.
1. The processor makes an internal copy of the status register (SR) and enters
2. The processor determines the exception vector number. For all faults except
3. The processor saves the current context by creating an exception stack frame on the
4. The processor calculates the address of the first instruction of the exception handler.
supervisor mode by setting SR[S] and disabling trace mode by clearing SR[T]. The
occurrence of an interrupt exception also forces the master mode (M) bit to clear and
the interrupt priority mask (I) to set to the level of the current interrupt request.
interrupts, the processor performs this calculation based on the exception type. For
interrupts, the processor performs an IACK bus cycle to obtain the vector number
from the interrupt controller if CPUCR[IAE] equals 1. The IACK cycle is mapped to
special locations within the interrupt controller's IPS address space with the interrupt
level encoded in the address. If CPUCR[IAE] equals 0, the processor uses the vector
number supplied by the interrupt controller at the time the request was signaled (for
improved performance).
system stack. As a result, exception stack frame is created at a 0-modulo-4 address
on top of the system stack defined by the supervisor stack pointer (SSP). The
processor uses an 8-byte stack frame for all exceptions. It contains the vector number
of the exception, the contents of the status register at the time of the exception, and
the program counter (PC) at the time of the exception. The exception type determines
whether the program counter placed in the exception stack frame defines the location
of the faulting instruction (fault) or the address of the next instruction to be executed
(next). For interrupts, the stacked PC is always the address of the next instruction to
be executed.
By definition, the exception vector table is aligned on a 1MB boundary. This
instruction address is generated by fetching a 32-bit exception vector from the table
located at the address defined in the vector base register (VBR). The index into the
exception table is calculated as (4 × vector number). After the exception vector has
been fetched, the contents of the vector serves as a 32-bit pointer to the address of the
first instruction of the desired handler. After the instruction fetch for the first opcode
of the handler has been initiated, exception processing terminates and normal
instruction processing continues in the handler.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 15 Interrupt Controller (INTC)
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