mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1319

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

50.4.3.1 Begin Execution of Taken Branch (PST = 0x05)
The PST is 0x05 when a taken branch is executed. For some opcodes, a branch target
address may be loaded into the trace buffer (PSTB) depending on the CSR settings. CSR
also controls the number of address bytes loaded that is indicated by the PST marker
value immediately preceding the DDATA entry in the PSTB that begins the address
entries.
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PST[4:0]
0x10–
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
Reserved
Completed execution of 2 sequential instructions
Completed execution of 3 sequential instructions
Completed execution of 4 sequential instructions
Completed execution of 5 sequential instructions
Completed execution of 6 sequential instructions
Completed execution of 7 sequential instructions
Completed execution of 8 sequential instructions
Completed execution of 9 sequential instructions
Completed execution of 10 sequential instructions
This value signals there has been a change in the breakpoint trigger state machine. It appears as a single
marker for each state change and is immediately followed by a DDATA value signaling the new breakpoint
trigger state encoding.
The DDATA breakpoint trigger state value is defined as (0x20 + 2 × CSR[BSTAT]):
0x20 No breakpoints enabled
0x22 Waiting for a level-1 breakpoint
0x24 Level-1 breakpoint triggered
0x2A Waiting for a level-2 breakpoint
0x2C Level-2 breakpoint triggered
Exception processing. This value signals the processor has encountered an exception condition. Although this is
a multi-cycle mode, there are only two PST = 0x1C values recorded before the mode value is suppressed.
Emulator mode exception processing. This value signals the processor has encountered a debug interrupt or a
properly-configured trace exception. Although this is a multi-cycle mode, there are only two PST = 0x1D values
recorded before the mode value is suppressed.
Processor is stopped. This value signals the processor has executed a STOP instruction. Although this is a
multi-cycle mode because the ColdFire processor remains stopped until an interrupt or reset occurs, there are
only two PST = 0x1E values recorded before the mode value is suppressed.
Processor is halted. This value signals the processor has been halted. Although this is a multi-cycle mode
because the ColdFire processor remains halted until a BDM go command is received or reset occurs, there are
only two PST = 0x1F values recorded before the mode value is suppressed.
Definition
Table 50-41. CF1 Debug Processor Status Encodings (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 50 Debug
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