mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1041

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

stop driving SDA output. In this case, the transition from master to slave mode does not
generate a STOP condition. Meanwhile, hardware sets a status bit to indicate the loss of
arbitration.
42.4.1.7 Clock Synchronization
Because wire AND logic is performed on SCL, a high-to-low transition on SCL affects
all devices connected on the bus. The devices start counting their low period and, after a
device's clock has gone low, that device holds SCL low until the clock reaches its high
state. However, the change of low to high in this device clock might not change the state
of SCL if another device clock is still within its low period. Therefore, the synchronized
clock SCL is held low by the device with the longest low period. Devices with shorter
low periods enter a high wait state during this time (see the following diagram). When all
applicable devices have counted off their low period, the synchronized clock SCL is
released and pulled high. Afterward there is no difference between the device clocks and
the state of SCL, and all devices start counting their high periods. The first device to
complete its high period pulls SCL low again.
42.4.1.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfers. A
slave device may hold SCL low after completing a single byte transfer (9 bits). In this
case, it halts the bus clock and forces the master clock into wait states until the slave
releases SCL.
Freescale Semiconductor, Inc.
S C L 1
S C L 2
S C L
In te rn a l C o u n te r R e s e t
Figure 42-63. I2C Clock Synchronization
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
D e la y
S ta rt C o u n tin g H ig h P e rio d
Chapter 42 Inter-Integrated Circuit (I2C)
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