mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 92

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

System modules
If the bus clock source is selected, the COP counter does not increment while the
microcontroller is in background debug mode or while the system is in stop (including
VLPS or LLS) mode. The COP counter resumes when the microcontroller exits
background debug mode or stop mode.
If the 1 kHz clock source is selected, the COP counter is re-initialized to zero upon entry
to either background debug mode or stop (including VLPS or LLS) mode. The counter
begins from zero upon exit from background debug mode or stop mode.
Regardless of the bus selected, the COP is disabled when the chip enters a VLLSx mode.
Upon a reset that wakes the chip from the VLLSx mode, the COP is re-initialized and
enabled as for any reset.
3.4.7 System Mode Controller (SMC) Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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System memory map
Power management
Full description
Topic
Low-Leakage Wakeup
Reset Control Module
Table 3-15. Reference links to related information
Figure 3-8. System Mode Controller configuration
Power management
Controller (SMC)
controller (PMC)
Related module
System Mode
Resets
Unit (LLWU)
(RCM)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Controller (SMC)
System Mode
Peripheral
Preliminary
bridge
Register
access
System memory map
Power management
Reference
LLWU
Reset
SMC
PMC
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