mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1296

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
1. This column identifies if the command generates an ACK pulse if operating with acknowledge mode enabled. See
2. The SYNC command is a special operation which does not have a command code.
3. If a GO command is received while the processor is not halted, it performs no operation.
50.4.1.5.1 SYNC
The SYNC command is unlike other BDC commands because the host does not
necessarily know the correct speed to use for serial communications until after it has
analyzed the response to the SYNC command.
To issue a SYNC command, the host:
1296
WRITE_CREG
WRITE_DREG
WRITE_MEM.sz
WRITE_MEM.sz_WS
WRITE_Rn
WRITE_XCSR_BYTE
WRITE_CSR2_BYTE
WRITE_CSR3_BYTE
Command
Mnemonic
1. Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock
2. Drives BKGD high for a brief speed-up pulse to get a fast rise time. (This speedup
3. Removes all drive to the BKGD pin so it reverts to high impedance.
4. Listens to the BKGD pin for the sync response pulse.
ACK_ENABLE
(bus clock or device-specific alternate clock source).
pulse is typically one cycle of the host clock which is as fast as the maximum target
BDC clock.)
, for addition information.
Always Available
Always Available
Always Available
Table 50-40. BDM Command Summary (continued)
Classification
Non-Intrusive
Non-Intrusive
Non-Intrusive
Background
Background
Command
Active
Active
MCF51JF128 Reference Manual, Rev. 2, 03/2011
if Enb?
ACK
Yes
Yes
Yes
Yes
No
No
No
No
1
Preliminary
(0x10+4 x sz)/ad24/wd.sz/
(0x11+4 x sz)/ad24/wd.sz/
(0xC0+CRN)/wd32/d
(0x80+CRN)/wd32/d
(0x40+CRN)/wd32/d
Command
0x0D/wd8
0x0E/wd8
0x0F/wd8
Structure
d/ss
d
Write one of the CPU's control
registers
Write one of the debug module's
control registers
Write the appropriately-sized (sz)
memory value to the location
specified by the 24-bit address
Write the appropriately-sized (sz)
memory value to the location
specified by the 24-bit address and
report status
Write the requested general-
purpose register (An, Dn) of the
CPU
Write the most significant byte of
the debug module's XCSR
Write the most significant byte of
the debug module's CSR2
Write the most significant byte of
the debug module's CSR3
Description
Freescale Semiconductor, Inc.