mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1259

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
12–11
Field
TRC
DDC
UHE
BTB
NPL
9–8
IPI
14
13
10
7
6
5
Force emulation mode on trace exception
0
1
Reserved; must be cleared.
Debug data control.
Controls peripheral bus operand data capture for DDATA, which displays the number of bytes
defined by the operand reference size (a marker) before the actual data; byte displays 8 bits, word
displays 16 bits, and long displays 32 bits (one nibble at a time across multiple PSTCLK clock
cycles). See Table 27-30. A non-zero value enables partial data trace capabilities.
00
01
10
11
User halt enable
Selects the CPU privilege level required to execute the HALT instruction. The core must be
operating with XCSR[ENBDM] set to execute any HALT instruction, else the instruction is treated
as an illegal opcode.
0
1
Branch target bytes
Defines the number of bytes of branch target address DDATA displays.
00
01
1x
Reserved; must be cleared.
Non-pipelined mode
Determines if the core operates in pipelined mode.
0
1
Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering
instruction executes. In normal pipeline operation, the occurrence of an address and/or data
breakpoint trigger is imprecise. In non-pipeline mode, these triggers are always reported before the
next instruction begins execution and trigger reporting can be considered precise.
Ignore pending interrupts when in single-step mode
0
1
Description
Table 50-6. CSR Field Descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Processor enters supervisor mode.
Processor enters emulator mode when a trace exception occurs.
No operand data is displayed.
Capture all write data.
Capture all read data.
Capture all read and write data.
HALT is a supervisor-only instruction.
HALT is a supervisor/user instruction.
No target address capture.
Lower 2 bytes of the target address
Lower 3 bytes of the target address
Pipelined mode
Non-pipelined mode. The processor effectively executes one instruction at a time with
no overlap. This typically adds five cycles to the execution time of each instruction.
Given an average execution latency of ~2 cycles per instruction, throughput in non-
pipeline mode would be ~7 cycles per instruction, approximately 25% - 33% of
pipelined performance.
Core services any pending interrupt requests signalled while in single-step mode.
Core ignores any pending interrupt requests signalled while in single-step mode.
Table continues on the next page...
Preliminary
Chapter 50 Debug
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