mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 161

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

6.2.2 System Reset Status Register 1 (RCM_SRS1)
This register includes read-only status flags to indicate the source of the most recent
reset. The reset state of these bits depends on what caused the MCU to reset.
Address: RCM_SRS1 is FFFF_8110h base + 1h offset = FFFF_8111h
Freescale Semiconductor, Inc.
SACKERR
Reserved
Reserved
Field
Reset
Field
Read
Write
7
6
5
Bit
The reset value of this register depends on the reset source:
Indicates a reset was caused by an enabled LLWU module wakeup source while the chip was in a low
leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any
enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except
WAKEUP.
0
1
This read-only bit is reserved and always has the value zero.
This read-only bit is reserved and always has the value zero.
Stop Mode Acknowledge Error Reset
Indicates a reset was caused, after an attempt to enter stop mode, by a failure of one or more peripherals
to acknowledge within approximately one second to enter stop mode.
0
1
7
0
0
• POR (including LVD) — 0x00
• LVD (without POR) — 0x00
• Low leakage wakeup (LLS mode exit via RESET pin or
• Other reset — a bit is set if its corresponding reset source
Reset not caused by LLWU module wakeup source
Reset caused by LLWU module wakeup source
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
any exit from VLLSx modes) — 0x00
caused the reset
RCM_SRS0 field descriptions (continued)
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
RCM_SRS1 field descriptions
SACKERR
Table continues on the next page...
0
5
Preliminary
NOTE
EZPT
0
4
Description
Description
BDFR
0
3
0
0
2
Chapter 6 Reset and Boot
0
0
1
0
0
0
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