mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1138

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

External signals
44.1.2.2 Stop Modes
In Stop Mode, the SAI Transmitter and/or Receiver can continue operating provided the
Stop Enable bit is set, and provided it is using an externally generated Bit Clock or an
Audio Master Clock that remains operating in Stop mode. The SAI Transmitter and/or
Receiver can generate an asynchronous interrupt to wakeup the CPU from Stop mode.
In Stop Mode, if the Transmitter Stop Enable bit is clear, the Transmitter is disabled after
completing the current transmit frame, and if the Receiver Stop Enable bit is clear, the
Receiver is disabled after completing the current receive frame.
44.1.2.3 Low-Leakage Modes
When entering low leakage modes, the Stop Enable bits are ignored and the SAI is
disabled after completing the current Transmit and Receive Frames.
44.1.2.4 Debug Mode
In Debug Mode, the SAI Transmitter and/or Receiver can continue operating provided
the Debug Enable bit is set. When the Transmitter or Receiver Debug Enable bit is clear
and Debug mode is entered, the SAI is disabled after completing the current Transmit or
Receive Frame. The Transmitter and Receiver bit clocks are not affected by debug mode.
44.2 External signals
1138
SAI_TX_BCLK
SAI_TX_SYNC
SAI_TX_DATA
SAI_RX_BCLK
SAI_RX_SYNC
SAI_RX_DATA
SAI_MCLK
Name
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Transmit Bit Clock
Transmit Frame Sync
Transmit Data
Receive Bit Clock
Receive Frame Sync
Receive Data
Audio Master Clock
Function
Preliminary
I/O
I/O
O
I/O
I/O
I
I/O
I/O
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
Reset
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Pull