mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1099

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

43.4.1.5 Idle characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character
length depends on the C1[M] and C1[PE] bits and the C4[M10] bit. The preamble is a
synchronizing idle character that begins the first transmission initiated after setting the
C2[TE] bit. When C7816[ISO_7816E] is set/enabled, idle characters are not sent or
detected. When data is not being transmitted the data I/O line is in an inactive state.
If the C2[TE] bit is cleared during a transmission, the transmit data output signal
becomes idle after completion of the transmission in progress. Clearing and then setting
the C2[TE] bit during a transmission queues an idle character to be sent after the
dataword currently being transmitted.
43.4.1.6 Hardware flow control
The transmitter supports hardware flow control by gating the transmission with the value
of CTS. If the clear-to-send operation is enabled, the character is transmitted when CTS
is asserted. If CTS is deasserted in the middle of a transmission with characters remaining
in the receiver data buffer, the character in the shift register is sent and TXD remains in
the mark state until CTS is reasserted.
Freescale Semiconductor, Inc.
When queuing a break character, it will be transmitted
following the completion of the data value currently being
shifted out from the shift register. This means that if data is
queued in the data buffer to be transmitted, the break character
will preempt that queued data. The queued data will then be
transmitted after the break character is complete.
When queuing an idle character the idle character will be
transmitted following the completion of the data value currently
being shifted out from the shift register. This means that if data
is queued in the data buffer to be transmitted, the idle character
will preempt that queued data. The queued data will then be
transmitted after the idle character is complete.
If the C2[TE] bit is cleared and the transmission is completed,
the UART is not the master of the TXD pin.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Chapter 43 Universal Asynchronous Receiver/Transmitter (UART)
Preliminary
NOTE
Note
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