mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 709

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

31.4.1 DAC Data Low Register (DACx_DATnL)
Addresses: FFFF_8500h base + 1h offset + (2d × n), where n = 0d to 15d
31.4.3 DAC Status Register (DACx_SR)
If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
request is done. Write zero to a bit to clear it. Writing one has no effect. After reset
DACBFRPTF is set and can be cleared by software, if needed. The flags are set only
when the data buffer status is changed.
Addresses: DAC0_SR is FFFF_8500h base + 20h offset = FFFF_8520h
Freescale Semiconductor, Inc.
DATA[11:8]
DATA[7:0]
Reserved
Field
Reset
Field
Reset
7–4
3–0
Read
7–0
Read
Write
Write
Bit
Bit
This read-only bitfield is reserved and always has the value zero.
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula. Vout = Vin * (1 + DACDAT0[11:0])/4096
When the DAC Buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula. Vout = Vin * (1 + DACDAT0[11:0])/4096
When the DAC Buffer is enabled, DATA is mapped to the 16-word buffer.
7
0
7
0
0
0
6
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
DACx_DATnH field descriptions
DACx_DATnL field descriptions
0
0
0
5
5
Preliminary
0
0
4
4
DATA[7:0]
Description
Description
Chapter 31 12-bit Digital-to-Analog Converter (DAC)
0
0
3
3
DACBFWMF
0
0
2
2
DACBFRPTF DACBFRPBF
0
1
1
1
0
0
0
0
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