mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 406

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Descriptions
18.5.1 Low Voltage Detect Status and Control 1 Register
This register contains status and control bits to support the low voltage detect function.
This register should be written during the reset initialization program to set the desired
controls even if the desired settings are the same as the reset settings.
While the device is in the very low power or low leakage modes, the LVD system is
disabled regardless of LVDSC1 settings. To protect systems that must have LVD always
on, configure the SMC's power mode protection register (PMPROT) to disallow any very
low power or low leakage modes from being enabled.
See the device's data sheet for the exact LVD trip voltages.
Address: PMC_LVDSC1 is FFFF_8100h base + 0h offset = FFFF_8100h
406
LVDACK
LVDIE
LVDF
Reset
Field
Read
Write
7
6
5
Bit
(PMC_LVDSC1)
The LVDV bits are reset solely on a POR Only event. The
register's other bits are reset on Chip Reset not VLLS. For more
information about these reset types, refer to the
LVDF
Low-Voltage Detect Flag
This read-only status bit indicates a low-voltage detect event.
0
1
Low-Voltage Detect Acknowledge
This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF). Reads
always return 0.
Low-Voltage Detect Interrupt Enable
Enables hardware interrupt requests for LVDF.
0
1
7
0
Low-voltage event not detected
Low-voltage event detected
Hardware interrupt disabled (use polling)
Request a hardware interrupt when LVDF = 1.
LVDACK
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
PMC_LVDSC1 field descriptions
Table continues on the next page...
LVDIE
0
5
Preliminary
NOTE
LVDRE
1
4
Description
0
3
0
Reset
0
2
details.
Freescale Semiconductor, Inc.
0
1
LVDV
0
0