mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 357

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 15 Interrupt Controller (INTC)
At the entry point (irqxx_entry), there is a two-instruction prologue to allocate space on
the supervisor stack to save the four volatile registers (d0, d1, a0, a1) defined in the
ColdFire application binary interface. After saving these registers, the ISR continues at
the alternate entry point.
The software IACK is performed near the end of the ISR, after the source of the current
interrupt request is negated. First, the appropriate memory-mapped byte location in the
interrupt controller is read (PC = 0x5C0). The CF1_INTC module returns the vector
number of the highest priority pending request. If no request is pending, zero is returned.
The compare instruction is needed to manage a special case involving pending level
seven requests. Because the level seven requests are non-maskable, the ISR is interrupted
to service one of these requests. To avoid any race conditions, this check ignores the level
seven vector numbers. The result is the conditional branch (PC = 0x5C8) is taken if there
are no pending requests or if the pending request is a level seven.
If there is a pending non-level seven request, execution continues with a three instruction
sequence to calculate and then branch to the appropriate alternate ISR entry point. This
sequence assumes the exception vector table is based at address 0x(00)00_0000 and that
each ISR uses the same two-instruction prologue shown here. The resulting alternate
entry point is a fixed offset (8 bytes) from the normal entry point defined in the exception
vector table.
The ISR epilogue includes a three instruction sequence to restore the volatile registers
from the stack and return from the interrupt exception.
This example is intentionally simple, but does show how performing the software IACK
and passing control to an alternate entry point when there is a pending but masked
interrupt request can avoid the execution of the ISR epilogue, another interrupt exception,
and the ISR prologue.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
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