mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 97

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mcf51jf128

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mcf51jf128
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Mcf51jf128 Reference Manual
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Freescale Semiconductor, Inc
Datasheet

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Chapter 3 Chip Configuration
3.6
Memories and Memory Interfaces
3.6.1 RAM Configuration
This section summarizes how the module has been configured in the chip.
Transfers
RAM
Figure 3-14. RAM configuration
Table 3-21. Reference links to related information
Topic
Related module
Reference
Description
RAM
RAM overview
System memory map
System memory map
Clocking
Clock distribution
Power management
Power management
3.6.1.1 RAM overview
The microcontroller includes up to 32 KB of static RAM. RAM is most efficiently
accessed using the A5-relative addressing mode (address register indirect with
displacement mode). Any single bit in this area can be accessed with the bit manipulation
instructions (BCLR, BSET, and so on).
At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset
provided that the supply voltage does not drop below the minimum value for RAM
retention (V
).
RAM
3.6.1.2 RAM sizes
The embedded RAM is tightly coupled with the V1 ColdFire core. The following table
describes the amount of RAM (not counting FlexRAM) for the chips covered by this
document.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
97

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