mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 441

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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20.3.6 MCG Control 6 Register (MCG_C6)
Address: MCG_C6 is FFFF_8400h base + 5h offset = FFFF_8405h
Freescale Semiconductor, Inc.
PRDIV
Field
Reset
4–0
Read
Write
Bit
LOLIE
Enables the PLL Clock during Normal Stop (In Low Power Stop mode, the PLL clock gets disabled even if
PLLSTEN=1). All other power modes, PLLSTEN bit has no affect and does not enable the PLL Clock to
run if it is written to 1.
0
1
PLL External Reference Divider
Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must
be in the range of 2 MHz to 4 MHz.
7
0
PRDIV
00000
00001
00010
00011
00100
00101
00110
00111
MCGPLLCLK is disabled in any of the Stop modes.
MCGPLLCLK is enabled if system is in Normal Stop mode.
Divide
Factor
1
2
3
4
5
6
7
8
PLLS
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
MCG_C5 field descriptions (continued)
Table 20-7. PLL External Reference Divide Factor
CME
0
5
PRDIV
01000
01001
01010
01011
01100
01101
01110
01111
Preliminary
Divide
Factor
9
10
11
12
13
14
15
16
0
4
Description
Chapter 20 Multipurpose Clock Generator (MCG)
0
3
PRDIV
10000
10001
10010
10011
10100
10101
10110
10111
Divide
Factor
17
18
19
20
21
22
23
24
VDIV
0
2
0
1
PRDIV
11000
11001
11010
11011
11100
11101
11110
11111
Divide
Factor
25
Reserv
ed
Reserv
ed
Reserv
ed
Reserv
ed
Reserv
ed
Reserv
ed
Reserv
ed
0
0
441

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