mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 886

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
37.4.22 Dual Edge Capture Mode
The dual edge capture mode is selected if FTMEN = 1 and DECAPEN = 1. This mode
allows to measure a pulse width or period of the signal on the input of channel (n) of a
channel pair. The channel (n) filter can be active in this mode when n is the channels 0 or
2.
The MS(n)A bit defines if the dual edge capture mode is one-shot or continuous
according to table "Mode, Edge, and Level Selection".
The ELS(n)B:ELS(n)A bits select the edge that is captured by channel (n), and ELS(n
+1)B:ELS(n+1)A bits select the edge that is captured by channel (n+1) as described in
table "Dual Edge Capture Mode — Edge Polarity Selection". If both ELS(n)B:ELS(n)A
and ELS(n+1)B:ELS(n+1)A bits select the same edge, then it is the period measurement.
If these bits select different edges, then it is a pulse width measurement.
In the dual edge capture mode, only channel (n) input is used and channel (n+1) input is
ignored.
886
CHnIE
system clock
channel (n) input
* Filtering function for dual edge capture mode is only available in the channels 0 and 2
0
1
CHnF bit is cleared either by the channel DMA transfer done or reading CnSC while CHnF is set and then
writing a logic 0 to CHnF bit.
CHnF bit is cleared by the channel DMA transfer done.
How CHnF Bit Can Be Cleared
Figure 37-210. Dual Edge Capture Mode Block Diagram
D
CLK
synchronizer
Q
Table 37-191. Clear CHnF Bit when DMA = 1
D
MCF51JF128 Reference Manual, Rev. 2, 03/2011
CLK
Q
Filter*
Preliminary
enabled?
is filter
0
1
ELS(n+1)B:ELS(n+1)A
ELS(n)B:ELS(n)A
Dual edge capture
DECAPEN
mode logic
FTMEN
DECAP
MS(n)A
FTM counter
CH(n+1)IE
CH(n+1)F
C(n+1)VH:L[15:0]
CH(n)IE
CH(n)F
C(n)VH:L[15:0]
Freescale Semiconductor, Inc.
channel (n+1)
channel (n)
interrupt
interrupt