mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 865

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

37.4.11.4 MODH:L Registers Synchronization
The MODH:L synchronization occurs when the MODH:L registers are updated with the
value of their write buffer.
The synchronization requires both bytes of MODH:L to have been written in one of the
following situations.
Freescale Semiconductor, Inc.
• If PWMSYNC = 0 and REINIT = 0, then the synchronization is made on the next
Figure 37-182. MODH:L Synchronization when (PWMSYNC = 0), (REINIT = 0), and
selected boundary cycle after an enabled trigger event takes place. If the trigger event
was a software trigger, then the SWSYNC bit is cleared on the next selected
boundary cycle (refer to the following figure).
If the trigger event was a hardware trigger, then the trigger enable bit (TRIGn) is
cleared when the trigger n event is detected (refer to the following figure).
selected boundary cycle
write 1 to SWSYNC bit
software trigger event
• PWM synchronization boundary cycle is only available
• PWM synchronization with (CNTMAX = 1) is not
when (CNTMIN = 1).
recommended and its results are not guaranteed.
SWSYNC bit
system clock
MCF51JF128 Reference Manual, Rev. 2, 03/2011
(Software Trigger Was Used)
Preliminary
Note
MODH:L registers
are updated if both bytes
were written
Chapter 37 FlexTimer (FTM)
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