mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 426

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
19.4 Functional Description
In the following discussion, the term DMA request implies that DCRn[START] is set, or
DCRn[ERQ] is set and then followed by assertion of the properly selected DMA
peripheral request. The START bit is cleared when the channel is activated.
Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE] and
DCRn[DSIZE] are consistent with the source and destination addresses. If they are not
consistent, the configuration error bit, DSRn[CE], is set. If misalignment is detected, no
transfer occurs, DSRn[CE] is set, and, depending on the DCR configuration, an interrupt
event may be issued. If the auto-align bit, DCRn[AA], is set, error checking is performed
on the appropriate registers.
A read/write transfer sequence reads data from the source address and writes it to the
destination address. The number of bytes transferred is the largest of the sizes specified
by DCRn[SSIZE] and DCRn[DSIZE] in the DMA Control Registers (DCRn).
Source and destination address registers (SARn and DARn) can be programmed in the
DCRn to increment at the completion of a successful transfer.
19.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)
The DMA channel supports software-initiated or peripheral-initiated requests. A request
is issued by setting DCRn[START] or when the selected peripheral request asserts and
DCRn[ERQ] is set. Setting DCRn[ERQ] enables recognition of the peripheral DMA
requests. Selecting between cycle-steal and continuous modes minimizes bus usage for
either type of request.
426
LCH2
Field
1–0
Link channel 2
Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as
the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).
00
01
10
11
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA_DCRn field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Description
Freescale Semiconductor, Inc.