mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 248

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
1. Fault refers to the PC of the instruction that caused the exception.
All ColdFire processors inhibit interrupt sampling during the first instruction of all
exception handlers. This allows any handler to disable interrupts effectively, if necessary,
by raising the interrupt mask level contained in the status register. In addition, the ISA_C
architecture includes an instruction (STLDSR) that stores the current interrupt mask level
and loads a value into the SR. This instruction is specifically intended for use as the first
instruction of an interrupt service routine that services multiple interrupt requests with
different interrupt levels. Finally, the V1 ColdFire core includes the CPUCR[IME] bit
that forces the processor to automatically raise the mask level to 7 during the interrupt
exception, removing the need for any explicit instruction in the service routine to perform
this function. For more details, see ColdFire Family Programmer's Reference Manual.
11.3.2.1 Exception Stack Frame Definition
The following figures shows the exception stack frame. The first longword contains the
16-bit format/vector word (F/V) and the 16-bit status register, and the second longword
contains the 32-bit program counter address.
The 16-bit format/vector word contains three unique fields:
248
• A 4-bit format field at the top of the system stack is always written with a value of 4,
Next refers to the PC of the instruction that follows the instruction that caused the fault.
SSP
5, 6, or 7 by the processor, indicating a two-longword frame format. See
11-15
Number(s)
+ 0x4
103–255
64–102
Vector
62–63
61
31 30 29 28 27
.
Format
Table 11-14. Exception Vector Assignments (continued)
FS[3:2]
26 25 24 23 22 21 20 19 18 17
Figure 11-2. Exception Stack Frame Form
0x19C–0x3FC
0x0F8–0x0FC
0x100–0x198
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Offset (Hex)
Vector
0x0F4
Vector
Preliminary
Program Counter
Stacked Program
FS[1:0]
Counter
16 15 14 13 12 11 10 9
Fault
Next
—
—
1
Status Register
Device-specific interrupts
Unsupported instruction
8
Freescale Semiconductor, Inc.
7
Assignment
Reserved
Reserved
6
5
4
Table
3
2
1
0