mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 258

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mcf51jf128

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mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Processor Exceptions
After the processor is granted the bus, it performs two longword read-bus cycles. The
first longword at address 0x(00)00_0000 is loaded into the supervisor stack pointer and
the second longword at address 0x(00)00_0004 is loaded into the program counter. After
the initial instruction is fetched from memory, program execution begins at the address in
the PC. If an access error or address error occurs before the first instruction is executed,
the processor enters the fault-on-fault state.
ColdFire processors load hardware configuration information into the D0 and D1
general-purpose registers after system reset. The hardware configuration information is
loaded immediately after the reset-in signal is negated. This allows an emulator to read
out the contents of these registers via the BDM to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in
Table
258
Reset
Reset
BDM:
11-19.
31–24
23–20
W
W
Field
VER
R
R
PF
Table 11-20. D0 Hardware Configuration Information Field Descriptions
31
15
1
0
0
Other implementation-specific registers are also affected. Refer
to each module in this reference manual for details on these
registers.
DIV
30
14
1
1
Table 11-19. D0 Hardware Configuration Information
Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.
ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core.
0001
Description
EMA
29
13
C
0
1
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
12
0
0
0
V1 ColdFire core
PF
27
11
1
0
0
Table continues on the next page...
Store: 0x40 (D0)
Load: 0x60 (D0)
CAU
26
10
1
1
Preliminary
25
1
9
0
0
Note
24
1
8
0
0
23
0
7
0
22
0
6
0
VER
ISA
21
0
5
1
20
1
4
0
Freescale Semiconductor, Inc.
19
Access: User read-only
3
1
BDM read-only
Device-specific
18
2
0
DEBUG
REV
17
1
0
16
0
1

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