mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 737

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
Reset
33.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)
Addresses: PDB0_CH0DLY0 is FFFF_8540h base + 18h offset = FFFF_8558h
33.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)
Addresses: PDB0_CH0DLY1 is FFFF_8540h base + 1Ch offset = FFFF_855Ch
Freescale Semiconductor, Inc.
Bit
Bit
W
W
R
R
Reserved
Reserved
31
31
0
0
31–16
31–16
15–0
15–0
Field
Field
DLY
DLY
30
30
0
0
29
29
0
0
28
28
0
0
This read-only bitfield is reserved and always has the value zero.
PDB Channel Delay
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts
when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective
for the current PDB cycle.
This read-only bitfield is reserved and always has the value zero.
PDB Channel Delay
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts
when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective
for the current PDB cycle.
27
27
0
0
26
26
0
0
25
25
0
0
24
24
0
0
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
23
0
0
PDBx_CHnDLY0 field descriptions
PDBx_CHnDLY1 field descriptions
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
Preliminary
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
Chapter 33 Programmable Delay Block (PDB)
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
DLY
DLY
0
0
7
7
0
0
6
6
0
0
5
5
4
0
4
0
0
0
3
3
0
0
2
2
0
0
1
1
737
0
0
0
0