mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 315

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

1. At end of reset, loaded with either 0000 or 1111 depending on flash option register bit 0 (FOPT[0])
13.2.21 Clock Divider 1 Register (SIM_CLKDIV1)
Address: SIM_CLKDIV1 is FFFF_80C0h base + 1Ch offset = FFFF_80DCh
Freescale Semiconductor, Inc.
USBFRAC
Reserved
USBSRC
USBDIV
Field
Reset
Field
Read
7–5
3–2
1–0
Write
4
Bit
1010
1011
1100
1101
1110
1111
USB clock divider divisor
Sets the divide value for the fractional clock divider used as a source for the USB clock. The source clock
for the fractional clock divider is set by the USBSRC register bit. Divider output clock = Divider input clock
* ( (USBFRAC+1) / (USBDIV+1) ).
USB clock divider fraction
Sets the fraction multiply value for the fractional clock divider used as a source for USB clock. The source
clock for the fractional clock divider is set by the USBSRC register bit. Divider output clock = Divider input
clock * ( (USBFRAC+1) / (USBDIV+1) )
This read-only bitfield is reserved and always has the value zero.
USB clock source select
00
01
10
11
7
0
Divided PLL (reset value)
Divided FLL
USB CLK pin
Reserved
Divide-by-11
Divide-by-12
Divide-by-13
Divide-by-14
Divide-by-15
Divide-by-16
USBDIV
SIM_CLKDIV0 field descriptions (continued)
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SIM_CLKDIV1 field descriptions
0
5
Preliminary
USBFRAC
0
4
Description
Description
0
3
Chapter 13 System Integration Module (SIM)
0
0
2
0
1
USBSRC
0
0
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