mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 756

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
The MTIM16 counter (CNTH:CNTL registers) has three modes of operation: stopped,
free-running, and modulo. The counter is stopped out of reset. If the counter starts
without writing a new value to the modulo registers, it will be in free-running mode. The
counter is in modulo mode when a value other than 0x0000 is in the modulo registers.
After an MCU reset, the counter stops and resets to 0x0000, and the modulo also resets to
0x0000. The bus clock functions as the default clock source, and the prescale value is
divided by 1. To start the MTIM16 in free-running mode, write to the MTIM16 status
and control (SC) register and clear the MTIM16 stop (TSTP) bit.
Four clock sources are software selectable: the internal bus clock, the fixed frequency
clock (XCLK), and an external clock on the TCLK pin that is selectable as incrementing
on either rising or falling edges. The MTIM16 clock select (CLKS) field in the CLK
register selects the desired clock source. If the counter is active (the TSTP bit is 0) when
a new clock source is selected, the counter continues counting from the previous value
using the new clock source.
Nine prescale values are software selectable: clock source divided by 1, 2, 4, 8, 16, 32,
64, 128, or 256. The prescaler select bits (PS[3:0]) in the CLK register select the desired
prescale value. If the counter is active (TSTP = 0) when a new prescaler value is selected,
the counter continues counting from the previous value using the new prescaler value.
The MTIM16 modulo register (MODH:MODL) allows the overflow compare value to be
set to any value from 0x0001 to 0xFFFF. Reset clears the modulo value to 0x0000, which
results in a free-running counter.
When the counter is active (the TSTP bit is 0), it increases at the selected rate until the
count matches the modulo value. When these values match, the counter overflows to
0x0000 and continues counting. The MTIM16 overflow flag (TOF) is set whenever the
counter overflows. The flag sets on the transition from the modulo value to 0x0000.
Clearing TOF is a two-step process. The first step is to read the SC register while TOF is
set. The second step is to write a 0 to TOF. If another overflow occurs between the first
and second steps, the clearing process is reset and TOF stays set after the second step is
performed. This will prevent the second occurrence from being missed. TOF is also
cleared when a 1 is written to TRST.
The MTIM16 module allows for an optional interrupt to be generated whenever TOF is
set. To enable the MTIM16 overflow interrupt, set the MTIM16 overflow interrupt
enable (TOIE) bit in the SC register. The TOIE bit should never be written to be 1 while
TOF is 1. Instead, TOF should be cleared first, and then the TOIE bit can be set to 1.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
756
Freescale Semiconductor, Inc.