mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 766

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
Functional description
35.3.4 Low Power Timer Counter Register (LPTMRx_CNR)
Addresses: LPTMR0_CNR is FFFF_84C0h base + Ch offset = FFFF_84CCh
35.4 Functional description
35.4.1 LPTMR power and reset
The LPTMR remains powered in all power modes, including low leakage modes. If the
LPTMR is not required to remain operating during a low power mode, then it should be
disabled before entering the mode.
The LPTMR is reset only on global POR or LVD. When configuring the LPTMR
registers, the control status register should be initially written with the timer disabled,
before configuring the LPTMR prescale register and compare register. The timer enable
should then be set as the last step in the initialization. This ensures the LPTMR is
configured correctly and the LPTMR counter is reset to zero following a warm reset.
35.4.2 LPTMR clocking
The LPTMR prescaler/glitch filter can be clocked by one of four clocks. The clock
source should be enabled before the LPTMR is enabled.
766
Bit
W
R
COUNTER
Reserved
31
0
31–16
15–0
Field
30
0
LPTMR1_CNR is FFFF_84D0h base + Ch offset = FFFF_84DCh
29
0
28
0
This read-only bitfield is reserved and always has the value zero.
Counter Value
The LPTMR Counter Register returns the value of the LPTMR counter at the time this register was last
written.
27
0
26
0
25
0
24
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
22
0
LPTMRx_CNR field descriptions
21
0
20
0
19
0
18
0
Preliminary
17
0
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
COUNTER
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
4
0
0
3
0
2
0
1
0
0