mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 556

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
The following figure shows the byte lanes that external memory connects to and the
sequential transfers of a 32-bit transfer for the supported port sizes when byte lane shift is
enabled.
24.4.4 Address/Data Bus Multiplexing
The interface supports a single 20-bit wide multiplexed address and data bus
(FB_AD[19:0]). The full 20-bit address is always driven on the first clock of a bus cycle.
During the data phase, the FB_AD[19:0] lines used for data are determined by the
programmed port size for the corresponding chip select. The device continues to drive the
address on any FB_AD[19:0] lines not used for data.
The table below lists the supported combinations of address and data bus widths.
24.4.5 Bus Cycle Execution
As shown in
556
Figure 24-12. Connections for External Memory Port Sizes (CSCRn[BLS] = 1)
Port Size & Phase
Figure 24-15
Table 24-13. Mini-FlexBus Multiplexed Operating Modes
Address phase
Address phase
Data phase
Data phase
Byte Select
32-Bit Port
16-Bit Port
8-Bit Port
Data Bus
External
Memory
Memory
Memory
MCF51JF128 Reference Manual, Rev. 2, 03/2011
and
Figure
FB_D[31:24]
FB_BE_7_0
Byte 0
address values
Driven with
24-17, basic bus operations occur in four clocks:
Preliminary
address values
FB_BE_15_8
FB_D[23:16]
Address
Driven with
[19:16]
Byte 1
FB_BE_23_16
Address
FB_D[15:8]
Byte 2
Byte 0
Byte 2
FB_BE_31_24
Address
Address
FB_D[7:0]
FB_AD
[15:8]
Byte 3
Byte 1
Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
Freescale Semiconductor, Inc.
Data
Data
[7:0]