MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 107

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

negate DSACKx within approximately one clock period after sensing the negation of AS or
DS.
4.4 CPU SPACE CYCLES
FC2–FC0 select user and supervisor program and data areas. The area selected by function
code FC3–FC0 = $7 is classified as the CPU space. The breakpoint acknowledge, LPSTOP
broadcast, module base address register access, and interrupt acknowledge cycles
described in the following paragraphs use CPU space. The CPU space type, which is
encoded on A19–A16 during a CPU space operation, indicates the function that the QUICC
is performing. On the QUICC, four of the encodings are implemented as shown in Figure 4-
22. All unused values are reserved by Motorola for additional CPU space types.
4.4.1 Breakpoint Acknowledge Cycle
The breakpoint acknowledge cycle allows external hardware to insert an instruction directly
into the instruction pipeline as the program executes. The breakpoint acknowledge cycle is
generated by the execution of the BKPT instruction, the internal breakpoint logic, or the
assertion of the BKPT pin. The T-bit state (shown in Figure 4-22) differentiates a software
breakpoint cycle (T = 0) from a hardware breakpoint cycle (T = 1).
When a software BKPT is executed, the QUICC performs a word read from CPU space, type
0, at an address corresponding to the breakpoint number (bits [2–0] of the BKPT opcode)
on A4–A2, and the T-bit (A1) is cleared. If this bus cycle is terminated with BERR (i.e., no
instruction word is available), the QUICC then performs illegal instruction exception pro-
cessing. If the bus cycle is terminated by DSACKx, the QUICC uses the data on the bus to
replace the BKPT instruction in the internal instruction pipeline and then begins execution
of that instruction.
REGISTER ACCESS
STOP BROADCAST
ACKNOWLEDGE
ACKNOWLEDGE
MODULE BASE
BREAKPOINT
LOW-POWER
INTERRUPT
ADDRESS
FUNCTION
3
3
3
3
0
0
0
0
CODE
Figure 4-22. CPU Space Address Encoding
1 1 1
1 1 1
1 1 1
1 1 1
Freescale Semiconductor, Inc.
0
0
0
0
For More Information On This Product,
31
31
31
31
0
0 0 0 0
1 1 1 1
0 0 0 0
0
MC68360 USER’S MANUAL
0
Go to: www.freescale.com
0
0
0 0 0 0
0 0 0 0
1 1 1 1
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1
CPU SPACE CYCLES
ADDRESS BUS
CPU SPACE
TYPE FIELD
19
19
19
19
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16
16
16
16
BKPT#
Bus Operation
LEVEL
T 0
0
0
0
0
1