MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 161

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.3.3.2 DATA MOVEMENT INSTRUCTIONS. The MOVE instruction is the basic means of
transferring and storing address and data. MOVE instructions transfer byte, word, and long-
word operands from memory to memory, memory to register, register to memory, and reg-
ister to register. Address movement instructions (MOVE or MOVEA) transfer word and long-
word operands and ensure that only valid address manipulations are executed.
In addition to the general MOVE instructions, there are several special data movement
instructions—move multiple registers (MOVEM), move peripheral data (MOVEP), move
quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective
address (PEA), link stack (LINK), and unlink stack (UNLK). Table 5-4 is a summary of the
data movement operations.
5.3.3.3 INTEGER ARITHMETIC OPERATIONS. The arithmetic operations include the four
basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as
arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction
set includes ADD, CMP, and SUB instructions for both address and data operations with all
Note: The following notations apply to this table only.
Instruction
MOVEM
MOVEQ
MOVEA
MOVEP
MOVE
UNLK
LINK
EXG
PEA
LEA
—
U
?
X
N
Z
V
Table 5-3. Condition Code Computations (Continued)
=
=
=
=
=
=
=
=
Dn, (d 16 , An)
(d 16 , An), Dn
# data Dn
Operand
An, # d
list, ea
ea , ea
Syntax
Rn, Rn
ea , An
ea , An
ea , list
Not affected
Undefined
See special definition
General case
C
Rm
Rm
Boolean AND
Boolean OR
Freescale Semiconductor, Inc.
An
ea
Table 5-4. Data Movement Operations
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16, 32
16, 32
Operand
8, 16, 32
8
16, 32
16, 32
16, 32
Size
32
32
32
32
32
32
32
Rn
SP – 4
Source
Source
Listed registers
Source
Dn [31:24]
(An + d)
Immediate Data
SP – 4
An
ea
Dn [15:8]
(An + d + 4)
SP; (SP)
Rn
An
Sm
Dm
Rm
R
n
r
LB
UB
Rm
SP, An
SP; ea
Destination
Destination
Listed registers
Dn [31:24]; (An + d + 2)
(An + d); Dn [23:16]
(An + d + 4); Dn [7:0]
= Source operand MSB
= Destination operand MSB
= Result operand MSB
= Register tested
= Bit Number
= Shift count
= Lower bound
= Upper bound
= NOT Rm
Dn [15:8]; (An + d + 6)
An, SP + 4
Destination
Destination
(SP); SP
Operation
SP
SP
An, SP + d
(An + d + 2);
Dn [23:16];
(An + d + 6)
Dn [7:0]
SP
CPU32+