MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 607

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

DM—Diagnostic Mode
TEN—SMC Transmit Enable
REN—SMC Receive Enable
7.11.7.12 SMC UART RECEIVE BUFFER DESCRIPTOR (RX BD). •The CP reports infor-
An example of the UART Rx BD process is shown in Figure 7-76. This figure shows the
resulting state of the Rx BDs after receipt of 10 characters, an idle period, and five charac-
ters—one with a framing error. The example assumes that MRBLR = 8 in the SMC param-
eter RAM.
E—Empty
Bits 14, 11, 10, 7, 6, 2—Reserved
1. Detection of an error during message processing
2. Detection of a full receive buffer
3. Reception of a programmable number of consecutive idle characters
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
00 = Normal operation
01 = Local loopback mode
10 = Echo mode
11 = Reserved
0 = SMC transmitter disabled
1 = SMC transmitter enabled
0 = SMC receiver disabled
1 = SMC receiver enabled
mation concerning the received data on a per-buffer basis via Rx BDs. The CP closes
the current buffer, generates a maskable interrupt, and starts to receive data into the
next buffer after one of the following events:
0 = The data buffer associated with this Rx BD has been filled with received data, or
1 = The data buffer associated with this BD is empty, or reception is currently in
data reception has been aborted due to an error condition. The CPU32+ core is
free to examine or write to any fields of this Rx BD. The CP will not use this BD
again while the E-bit remains zero.
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E-bit is set, the CPU32+ core should not write any fields of this Rx BD.
15
E
14
—
13
Freescale Semiconductor, Inc.
W
For More Information On This Product,
12
I
MC68360 USER’S MANUAL
Go to: www.freescale.com
11
—
10
—
CM
RX DATA BUFFER POINTER
9
DATA LENGTH
ID
8
—
7
Serial Management Controllers (SMCs)
—
6
BR
5
FR
4
PR
3
—
2
OV
1
CD
0