MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 361

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

W—Wrap (Final BD in Table)
I—Interrupt
L—Last
CM—Continuous Mode
The following bits are written by the RISC controller after it has finished receiving data from
the associated data buffer.
SE—Source Access Bus Error
The buffer was closed due to a bus error on the source access. An interrupt (BES) will be
generated, regardless of the I-bit. The RISC will clear the V-bit of this BD.
0 = This is not the last BD in the table.
1 = This is the last BD in the table. After the associated buffer has been used, the RISC
0 = No interrupt is generated after this buffer has been serviced.
1 = When this buffer has been serviced by the RISC controller the AD bit in the CSR
0 = This is not the last buffer to be transferred in the buffer chaining mode. The I-bit
1 = This is the last buffer to be transferred in the buffer chaining mode. When the trans-
0 = Buffer chaining mode. The RISC will clear the V-bit after this BD is serviced. The
1 = Auto buffer mode (continuous mode). The RISC will not clear the V-bit after this BD
controller will transfer data from the first BD in the table (pointed to by IBASE). The
number of BDs in this table is programmable and is determined only by the W-bit
and the overall space constraints of the dual-port RAM.
will be set, which can cause an interrupt.
may be used to generate an interrupt when this buffer has been serviced.
fer count is exhausted, the START bit will be reset and an interrupt (DONE) will be
generated, regardless of the I-bit.
buffer chaining mode is used for transferring large quantities of data into noncon-
tiguous buffer areas. The user can initialize BDs ahead of time, if desired. The
RISC controller automatically reloads the IDMA registers from the next BD’s values
when the transfer is terminated. If DONEx is asserted by an external peripheral,
the buffer will be closed, the STR bit will be reset, and the DONE bit will be set in
the CSR, which can cause an interrupt.
is serviced. This is the only difference between auto buffer mode and buffer chain-
ing mode behavior. The auto buffer mode is used to transfer multiple groups of data
to/from a buffer ring. This mode does not require reprogramming. The RISC con-
troller automatically reloads the IDMA registers from the next BD values when the
transfer is terminated. Either a single BD or multiple BDs may be used in this mode
to create an infinite loop of repeated data moves.
The I-bit may still be used to generate an interrupt in this mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
IDMA Channels