MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 937

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Figure D-5 shows the line interface unit, LIU, being the master and providing the QUICC32
with clocks. It is also possible to let the QUICC32 be the master and provide clocks and syn-
chronization pulses through its baud rate generators, both to itself and other devices on the
TDM bus.
D.2.4 The QMC Microcode
The standard QUICC can handle one logical channel performing the protocol framework for
each of its serial channels. This logical channel can be used in time division multiplexed
interfaces as described above. The QMC protocol emulates up to 32 serial controllers that
can operate in either HDLC mode or transparent mode within one single SCC.
The QMC microcode is ROM based and in order to create enough memory space, the
QUICC32 has the Centronics and BISYNC protocols removed.
The QUICC32 has the internal dual-port RAM enlarged by 192 bytes to accommodate the
parameters used by the QMC microcode.
The standard QUICC housed all the buffer descriptor table in internal RAM and the actual
data areas in either internal or external RAM. The QUICC32 needs an area in external mem-
ory for its buffer descriptor. This reserved memory area shall start at an address on a 64 K
boundary. The data buffers have to reside in external main memory. See Figure D-6 for
memory partitioning.
Freescale Semiconductor, Inc.
For More Information On This Product,
LIU
Figure D-5. TDM Connections
MC68360 USER’S MANUAL
Go to: www.freescale.com
Tx
Rx
Rx AND Tx CLOCKS AND FRAME SYNCHRONIZATION
OTHER SYSTEM
FUNCTIONS
QUICC32
MC68MH360 Product Brief
OTHER PCM
LINE DEVICES