MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 665

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

T/R—Transmit/Receive Select
7.13.7.3 PIP TIMING PARAMETERS REGISTER (PTPR). The PTPR is a 16-bit read-write
register that is cleared at reset. The PTPR holds two timing parameters, TPAR1 and TPAR2,
which are used in the pulsed handshake modes for both a PIP transmitter and a receiver.
TPAR1—Timing Parameter 1
TPAR2—Timing Parameter 2
7.13.7.4 PIP BUFFER DESCRIPTORS. BDs for the receiver and transmitter that support
PIP operation were still in preparation at the time of writing.
7.13.7.5 PIP EVENT REGISTER (PIPE). The PIPE is an 8-bit register used to report events
recognized by the PIP and to generate interrupts. It shares the same address as the SMC2
event register; thus, SMC2 cannot be used simultaneously with the PIP. Upon recognition
of an event, the PIP sets its corresponding bit in the PIPE. Interrupts generated by this reg-
ister may be masked in the PIP mask register.
The PIPE is a memory-mapped register that may be read at any time. A bit is cleared by
writing a one (writing a zero does not affect a bit’s value). More than one bit may be cleared
at a time. All unmasked bits must be cleared before the CP will clear the internal interrupt
request. This register is cleared at reset.
Bits 7–4—Reserved
CCR—Control Character Received
This bit selects transmitter or receiver operation for the PIP when it is using the inter-
locked, pulsed, or transparent handshake modes.
15
This 8-bit value defines the number of system clocks for TPAR1 in the transmitter or re-
ceiver pulsed handshake mode. The value $00 corresponds to 1 QUICC general system
clock, and the value $FF corresponds to 256 QUICC general system clocks. A general
system clock defaults to 40 ns, assuming a 25-MHz QUICC system.
This 8-bit value defines the number of system clocks for TPAR2 in the transmitter or re-
ceiver pulsed handshake mode. The value $00 corresponds to 1 QUICC general system
clock, and the value $FF corresponds to 256 QUICC general system clocks. A general
system clock defaults to 40 ns, assuming a 25-MHz QUICC system.
A control character was received (with reject (R) = 1) and stored in the receive control
character register.
0 = Data is input to the PIP.
1 = Data is output from the PIP.
14
13
12
TPAR2
Freescale Semiconductor, Inc.
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For More Information On This Product,
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MC68360 USER’S MANUAL
—
Go to: www.freescale.com
5
9
8
4
CCR
3
7
BSY
6
2
CHR
5
1
BD
4
0
TPAR1
Parallel Interface Port (PIP)
3
2
1
0