MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 121

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The QUICC retries any read or write cycle of a read-modify-write operation separately; RMC
remains asserted during the entire retry sequence.
Asserting BR at the same time as BERR and HALT provides a relinquish and retry opera-
tion. The QUICC does not relinquish the bus during a read-modify-write cycle, but may relin-
quish the bus between any other bus cycles. (i.e. relinquish-and-retry has priority over bus
coherency, except in the case of read-modify-write cycles). Any device that requires the
QUICC to give up the bus and retry a bus cycle during a read-modify-write cycle must assert
BERR and BR only (HALT must not be included). The bus error handler software should
examine the read-modify-write bit in the special status word (refer to Section 5 CPU32+) and
take the appropriate action to resolve this type of fault when it occurs.
FC3–FC0
DSACKx
A31–A0
D31–D0
CLKO1
BERR
HALT
R/W
AS
DS
When the relinquish and retry is asserted during an internal mas-
ter's word access to an 8-bit port, and the external master that
takes the bus performs an external-to-internal bus cycle, the en-
S0
Freescale Semiconductor, Inc.
S2
For More Information On This Product,
READ CYCLE WITH
Figure 4-31. Retry Sequence
SW
RETRY
MC68360 USER’S MANUAL
Go to: www.freescale.com
IGNORED
SW
DATA
NOTE
S4
HALT
S0
READ RERUN
S2
S4
Bus Operation