MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 201

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.6 DEVELOPMENT SUPPORT
All M68000 family members have the following special features that facilitate applications
development.
Trace on Instruction Execution—All M68000 processors include an instruction-by-instruc-
tion tracing facility to aid in program development. The MC68020, MC68030, and CPU32+
can also trace those instructions that change program flow. In trace mode, an exception is
generated after each instruction is executed, allowing a debugger program to monitor exe-
cution of a program under test. See 5.5.2.10 Tracing for more information.
Breakpoint Instruction—An emulator can insert software breakpoints into target code to indi-
cate when a breakpoint occurs. On the MC68010, MC68020, MC68030, and CPU32+, this
function is provided via illegal instructions ($4848–$484F) that serve as breakpoint instruc-
tions. See 5.5.2.5 Software Breakpoints for more information.
Unimplemented Instruction Emulation—When an attempt is made to execute an illegal
instruction, an illegal instruction exception occurs. Unimplemented instructions (F-line, A-
line) utilize separate exception vectors to permit efficient emulation of unimplemented
instructions in software. See 5.5.2.8 Illegal or Unimplemented Instructions for more informa-
tion.
5.6.1 CPU32+ Integrated Development Support
In addition to standard MC68000 family capabilities, the CPU32+ has features to support
advanced integrated system development. These features include background debug
mode, deterministic opcode tracking, hardware breakpoints, and internal visibility in a sin-
gle-chip environment.
5.6.1.1 BACKGROUND DEBUG MODE (BDM) OVERVIEW. Microprocessor
generally provide a debugger, implemented in software, for system analysis at the lowest
level. The BDM on the CPU32+ is unique because the debugger is implemented in CPU
microcode.
BDM incorporates a full set of debug options—registers can be viewed and/or altered, mem-
ory can be read or written, and test features can be invoked.
A resident debugger simplifies implementation of an in-circuit emulator. In a common setup
(see Figure 5-18), emulator hardware replaces the target system processor. A complex,
expensive pod-and-cable interface provides a communication path between target system
and emulator.
TARGET
SYSTEM
Figure 5-18. In-Circuit Emulator Configuration
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
IN-CIRCUIT
EMULATOR
TARGET
MCU
systems
CPU32+