MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 165

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.3.3.6 BIT MANIPULATION INSTRUCTIONS. Bit manipulation operations are accom-
plished using the following instructions: bit test (BTST), bit test and set (BSET), bit test and
clear (BCLR), and bit test and change (BCHG). All bit manipulation operations can be per-
formed on either registers or memory. The bit number is specified as immediate data or in
a data register. Register operands are 32 bits, and memory operands are 8 bits. Table 5-8
is a summary of bit manipulation instructions.
Instruction
ROXR
SWAP
ROXL
ROR
ASR
ROL
ASL
LSR
LSL
# data Dn
# data Dn
# data Dn
# data Dn
# data Dn
# data Dn
# data Dn
# data Dn
Operand
Syntax
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Freescale Semiconductor, Inc.
ea
Dn
ea
ea
ea
ea
ea
ea
ea
Table 5-7. Shift and Rotate Operations
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Operand
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
Size
16
16
16
16
16
16
16
16
16
C
0
X/C
X
X/C
C
Operation
MSW
LSW
X/C
C
X/C
X
0
0
C
CPU32+