MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 662

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Parallel Interface Port (PIP)
7.13.6 Transparent Data Transfers
In the transparent handshake mode, the PIP may be configured as a transmitter or a
receiver. This configuration has only one handshake pin.
The transparent mode is controlled only by the RISC. Operation using the RISC requires
BDs and parameter RAM initialization very similar to the other serial channels. Data is then
stored in the buffers using one of the SDMA channels (one of the available channels from
SMC2).
In this mode, the B17 pin falling edge generates the request to the RISC, which causes the
RISC to receive/transmit data. The direction of the pins is controlled by the port B data direc-
tion register (PBDIR). The transparent handshake mode is shown in Figure 7-93.
7.13.7 Programming Model
The following paragraphs describe the PIP registers and parameter RAM.
7.13.7.1 PARAMETER RAM. At the time of writing, RISC operation on the PIP has not been
fully defined. The user should use the CPU32+ core operation mode until the RISC micro-
code becomes available or the full PIP microcode becomes available in the RISC internal
ROM. Please contact the local Motorola sales representative to obtain the current status of
the PIP RISC microcode.
7-338
At the time of writing, this operation of the PIP has not been fully
defined. This PIP operation may be implemented by the
CPU32+ core, using the port B parallel I/O registers and any port
C interrupt pin.
Figure 7-93. PIP Transparent Handshake Mode
READ FROM RISC
WRITE FROM RISC
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
BUFFER
LATCH
Go to: www.freescale.com
NOTE
DIR = OUTPUT
I/O
PIN