MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 635

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

C/I DATA—Command/Indication Data Bits
7.11.14.8 SMC C/I CHANNEL TRANSMIT BUFFER DESCRIPTOR (TX BD). The
reports information about the C/I channel transmit byte using the BD.
R—Ready
Bits 14–6—Reserved
C/I DATA—Command/Indication Data Bits
7.11.14.9 SMC EVENT REGISTER (SMCE). The SMCE is an 8-bit register used to report
events recognized by the SMC channel and to generate interrupts. On recognition of event,
the SMC sets its corresponding bit in this register. Interrupts generated by this register may
be masked in the SMC mode register.
The SMCE is a memory-mapped register that may be read at any time. A bit is cleared by
writing a one (writing a zero does not affect a bit’s value). More than one bit may be cleared
at a time. All unmasked bits must be cleared before the CP will clear the internal interrupt
request to the CPM interrupt controller. This register is cleared at reset.
Bits 7–4—Reserved
CTXB—C/I Channel Buffer Transmitted
C/I DATA is a 4-bit data field for C/I channel 0 and a 6-bit data field for C/I channel 1. It
contains the data received from the C/I channel. For C/I channel 0, bits 5-2 contain the 4-
bit data field, and bits 7 and 6 are always written with zeros. For C/I channel 1, bits 7-2
contain the 6-bit data field..
15
These bits should be cleared by the user.
C/I DATA is a 4-bit data field for C/I channel 0 and a 6-bit data field for C/I channel 1. It
contains the data to be transmitted onto the C/I channel. For C/I channel 0, bits 5-2 con-
tain the 4-bit data field, and bits 7 and 6 are always written with zeros. For C/I channel 1,
bits 7-2 contain the 6-bit data field.
The C/I transmit buffer became empty.
R
0 = This bit is cleared by the CP after transmission to indicate that the BD is now avail-
1 = This bit is set by the CPU32+ core to indicate that the data associated with this BD
14
able to the CPU32+ core.
is ready for transmission.
—
INITIAL VALUE:
7
13
—
6
12
—
5
Freescale Semiconductor, Inc.
11
—
For More Information On This Product,
—
4
10
CTXB
MC68360 USER’S MANUAL
Go to: www.freescale.com
3
9
CRXB
2
8
MTXB
1
7
0
MRXB
0
6
0
Serial Management Controllers (SMCs)
5
0
C/I DATA
4
0
3
2
1
—
CP
0