MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 123

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

When the QUICC completes a bus cycle with HALT asserted, D31–D0 is placed in the high-
impedance state, and bus control signals are driven inactive (not high-impedance state); the
address, function code, size, and read/write signals remain in the same state. The halt oper-
ation has no effect on bus arbitration (refer to 4.6 Bus Arbitration). When bus arbitration
occurs while the QUICC is halted, the address and control signals are also placed in the
high-impedance state. Once bus mastership is returned to the QUICC, if HALT is still
asserted, the address, function code, size, and read/write signals are again driven to their
previous states. The QUICC does not service interrupt requests while it is halted.
In Figure 4-33, note that BR is not asserted until after the halt op-
eration is complete. If BR is asserted at the same time as HALT,
the user should note that the BG signal may not be asserted im-
mediately (as in other M68000 family devices) but rather after
the full operand transfer is complete. This difference in behavior
is due to the coherency rules imposed by the QUICC and other
IMB-based M68300 family members. Refer to 4.6 Bus Arbitra-
tion for more details. To override the coherency rules, a relin-
quish and retry cycle may be used.
In the MCR of the SIM60, if the show cycles enable bits SHEN1-
SHEN0 = 1x to enable show cycles mode, and HALT is asserted
externally, the following behavior is possible. It is possible that
the QUICC may not show the last bus cycle externally, if that bus
cycle happens to be an internal-to-internal bus cycle. This is due
to a pipelining characteristic of the QUICC coupled with the
HALT signal being asserted late into an internal-to-external bus
cycle. Note that show cycles mode is not the normal configura-
tion for the QUICC.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
Bus Operation