MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 271

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

6.8.6 Other Functionality in Slave Mode
Although the slave mode does enable a number of different pins on the system bus and
causes functional activities such as bus arbitration and interrupt handling to occur differ-
ently, if a feature is not cited as changing its behavior in slave mode (i.e., 98% of the features
on QUICC), then it is not impacted by slave mode and continues to operate normally.
6.9 PROGRAMMER’S MODEL
The SIM60 contains a number of registers, described in the following paragraphs. Their
locations and initial values may be found in Section 3 QUICC Memory Map.
6.9.1 Module Base Address Register (MBAR)
The MBAR is a 32-bit, memory-mapped, read-write register consisting of the high address
bits. Upon a total system reset, its value may be read as $0. The address of this register is
fixed at $03FF00 in CPU space (except in slave mode where it is located at $03FF04). See
6.8 Slave (Disable CPU32+) Mode for details.
BA31–BA13—Base Address
AS8–AS0—Address Space
RESET:
RESET:
BA31
BA15
31
15
The base address field is the upper 19 bits of the MBAR, providing for block starting loca-
tions in increments of 8 Kbytes.
The address space field allows particular address spaces to be masked, placing the 8K
module block into a particular address space(s). If an address space is masked, an ac-
cess to the register block location in that address space becomes an external access. The
module block is not accessed. The address space bits for non-040 type master are:
1. AS8—mask DMA space address space (FC3–FC0=1xxx)
2. AS7—mask CPU space address space (FC3–FC0=0111)
3. AS6—mask supervisor program address space (FC3–FC0=0110)
0
0
the QUICC is in slave mode, assertion of the TS pin notifies the QUICC that an exter-
nal MC68040 cycle is beginning. Although the user typically configures the CONFIGx
pins for MC68040 companion mode, this configuration is not required. It is possible for
the QUICC to recognize an MC68040 cycle in any of the slave mode variations. (The
reason for the MC68040 companion mode configuration of the CONFIGx pins is to al-
low the bus arbitration pins to have their directions reversed while still in slave mode.)
BA30
BA14
30
14
0
0
BA29
BA13
29
13
0
0
BA28
28
12
0
0
0
Freescale Semiconductor, Inc.
BA27
27
11
0
0
0
For More Information On This Product,
BA26
26
10
0
0
0
MC68360 USER’S MANUAL
Go to: www.freescale.com
BA25
AS8
25
0
9
0
BA24
AS7
24
0
8
0
BA23
AS6
23
0
7
0
BA22
AS5
22
0
6
0
BA21
AS4
21
System Integration Module (SIM60)
0
5
0
BA20
AS3
20
0
0
4
BA19
AS2
19
0
3
0
BA18
AS1
18
0
2
0
CPU SPACE ONLY
BA17
AS0
17
0
1
0
BA16
16
V
0
0
0