MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 770

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Applications
The memory controller status register (MSTAT) is used for reporting write protect and parity
errors and does not require initialization.
The eight base registers (BRs), one for each memory bank, should be configured as follows:
The eight option registers (ORs), one for each memory bank, should be configured as fol-
lows:
9-50
SYNC is not used in this design since there is only one QUICC. It should be cleared.
OPAR may be chosen by the user.
PBEE should be cleared because parity errors should not generate bus errors in
MC68040 companion mode.
TSS40 should be set to meet MC68EC040 electrical specification 11. However, it may be
cleared for faster operation if spec 11 is reduced from 30 ns to 25 ns because of a lightly
loaded MC68EC040 bus.
NCS should normally be set.
DWQ should be cleared since page mode is not allowed in MC68040 companion mode.
DW40 depends on the timing analysis.
AMUX should be cleared.
The BA27–BA11 bits may be set as desired. Different memory arrays should not overlap.
BA31–BA28 should be cleared since the byte write lines are used with an external master
in the system.
For simplicity, FC3–FC0 can be cleared.
TRLXQ should normally be cleared for memory interfaces.
BACK40 should be set if the QUICC provides bursting for the MC68EC040 accesses to
standard SRAM and DRAM.
CSNT40 should normally be set.
CSNTQ should normally be cleared.
PAREN should be set for memory banks that use parity.
WP should be set for EPROM, burst EPROM, and flash EPROM; otherwise, it should be
cleared.
V should be set if the memory bank is used.
The TCYC bits should be set to determine the number of wait states required.
The AM27–AM11 bits should be set to determine the block size of the chip select or RASx
line. This should be the total number of bytes in each memory array except the EEPROM,
which should be 32 Kbytes rather than 8 Kbytes.
FCM3–FCM0 may be set to all zeros to allow the chip select or RASx line to assert on all
function codes except CPU space (interrupt acknowledge). It is advisable to program
FCM3–FCM0 to zeros, at least during the initial stages of debugging.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com