MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 721

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
SECTION 9
APPLICATIONS
9.1 MINIMUM SYSTEM CONFIGURATION
This section describes a basic minimum system configuration for the QUICC. It discusses
the hardware and software issues of configurating the QUICC to support a basic system with
a variety of ROM and RAM types.
9.1.1 QUICC Hardware Configuration
These paragraphs discuss the hardware issues relating to the configuration of the QUICC.
Reference Figure 9-1 during these discussions. This configuration assumes a 32-bit data
bus. Comments about the changes required for a 16-bit data bus solution are given at the
end of the discussion.
9.1.1.1 QUICC BASIC ACCESSES. The basic connection is made through the data and
address bus. All 32 data lines are used in this application, although not all memories are a
full 32-bits wide.
Twenty-eight address lines are used, giving a 256-Mbytes address capability. It is possible
to use all 32 address lines, but the QUICC would then lose its write enable lines (WE3–
WE0). Since these lines are very useful in memory interfaces, they are used in the applica-
tion.
The function code (FC3–FC0) and data strobe (DS) lines are shown routed to the system
bus, although the memories in this application do not require them.
Other pins not directly needed are DSACKx, BERR, SIZx, PERR, IPIPEx, and a number of
chip selects. The DSACKx lines are not required because the on-chip wait state generator
is used. The BERR pin is not needed because all bus errors are generated by internal mon-
itor logic. The SIZx pins are not needed because the memory controller has programmable
port sizes for each memory bank. The PERR pin is not needed because parity errors gen-
erate bus errors. The IPIPEx pins are only needed for emulator support. The additional chip
selects can be used to add additional peripherals as required.
MC68360 USER’S MANUAL
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