MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 139

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

4.7 RESET OPERATION
The QUICC has reset control logic to determine the cause of reset, synchronize it if neces-
sary, and assert the appropriate reset lines. The reset control logic can independently drive
five different internal lines:
Table 4-9 summarizes the result of each reset source. Synchronous reset sources are not
asserted until the end of the current bus cycle, regardless of whether RMC is asserted. The
internal bus monitor is automatically enabled for synchronous resets; therefore, if the current
bus cycle does not terminate normally, the bus monitor terminates it. Only single-byte or
word transfers are guaranteed valid for synchronous resets. Asynchronous reset sources
indicate a catastrophic failure, and the reset controller logic immediately resets the system.
Resetting the QUICC causes any bus cycle in progress to terminate as if DSACKx or BERR
had been asserted. In addition, the QUICC appropriately initializes registers for a reset
exception.
1. EXTSYSRST (external system reset) drives the external hard and soft reset pins (RE-
2. EXTRST (external reset) drives the external soft reset pin (RESETS).
3. CLKRST (clock reset) resets the clock module.
4. INTSYSRST (internal system reset) resets the memory controller, system protection
5. INTRST (internal reset) goes to all other internal circuits.
SETH and RESETS).
logic, serial interface, interrupt controller, and parallel I/O modules.
SIZ1–SIZ0
Figure 4-45. Show Cycle Timing Diagram
FC3–FC0
Freescale Semiconductor, Inc.
D31–D0
A31–A0
CLKO1
AS, CS
BKPT
For More Information On This Product,
R/W
DS
S0
MC68360 USER’S MANUAL
Go to: www.freescale.com
SHOW CYCLE
S41
S42
S43
S0
EXTERNAL CYCLE
START OF
S1
S2
Bus Operation