MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 663

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.13.7.2 PIP CONFIGURATION REGISTER (PIPC). The PIPC is a 16-bit read-write regis-
ter that is cleared at reset. The PIPC determines all PIP options.
STR —Start (Valid for a Transmitter Only)
Bits 14–12—Reserved
SACK—Set Acknowledge
CBSY—Clear BUSY
SBSY—Set BUSY
EBSY—Enable BUSY (Receiver)
STR
15
This bit is valid only when the T/R bit is set to 1 (transmitter). Setting this bit to 1 causes
the RISC controller to poll the Tx BD. Thus, the user should prepare a Tx BD and set its
R- bit before setting STR. STR is cleared after one system clock.
When set, this bit will assert the receiver’s ACK output (low voltage), regardless of the re-
ceiver’s state. SACK should be used when implementing the IEEE P1284 Bidirectional
Centronics protocol.
This bit is used by host software to force the BUSY signal low for a Centronics receiver.
When CBSY is set, the BUSY signal will output at 0 (low voltage). CBSY is cleared after
the PIP negates the BUSY signal.
This bit is used by host software to force the BUSY signal high for a Centronics receiver.
When SBSY is set, the BUSY signal will output a 1 (high voltage). SBSY is cleared after
the PIP asserts the BUSY signal.
This bit has a different definition depending on whether T/R is set to receiver or transmit-
ter.
When T/R = 0 (PIP is a receiver), the definition is as follows:
0 = Disable BUSY signal generation on PB0 for the receiver.
1 = Enable the BUSY output signal on PB0. EBSY will only take effect if bit 0 of PBPAR
14
is 0 to configure this pin to belong to the PIP and bit 0 of PBDIR is 1 to make this
pin an output.
13
The T/R bit should be set to 0 (receiver) if CBSY is used.
The T/R bit should be set to 0 (receiver) if SBSY is used. Also,
EBSY would normally be set by the user before SBSY is set. (If
EBSY is cleared, the PIP ignores the STB signal until CBSY is
set in software.)
—
12
Freescale Semiconductor, Inc.
SACK
11
For More Information On This Product,
CBSY
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
SBSY
9
EBSY
NOTE
NOTE
8
7
TMOD
6
5
MODL
4
Parallel Interface Port (PIP)
3
MODH
2
HSC
1
T/R
0