MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 729

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9.1.2.7 DRAM DEVICES. Figure 9-7 shows the glueless interface to standalone DRAM
devices. In this case, the MCM54260 256K
32-bit-wide DRAM solution using only two DRAM devices, with byte writes still supported
using the upper and lower CAS pins. The RAS1 line should be programmed to respond to
a 1-Mbyte address space.
The address multiplexing scheme shown is the same as that for the DRAM SIMM. No parity
support is provided in this case. The RAS1DD signal is not used in this case since only two
devices are supported.
After power-on reset, the software must wait the required time before accessing the DRAM.
The required eight read cycles must be performed either in software or by waiting for the
refresh controller to perform these accesses.
Figure 9-6. Glueless Interface to MCM36100S SRAM
SYSTEM BUS
AND
QUICC-GENERATED
SIGNALS
A11—A2
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
D23—D16
D31—D24
RAS1DD
D15—D8
D7—D0
PRTY3
PRTY2
PRTY0
PRTY1
CAS3
CAS2
CAS1
CAS0
RAS1
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
R/W
A0
A1
A2
A3
A7
A8
RAS0
CAS1
DQ35
A4
A5
A6
A9
RAS2
CAS0
CAS2
CAS3
W
DQ7—DQ0
DQ8
DQ16—DQ9
DQ17
DQ25—DQ18
DQ26
DQ34—DQ27
16 DRAM device is chosen. This allows a full
1M 36 BIT DRAM
1M 1
1M 1
1M 1
1M 1
MCM36100S
MODULE
1M 4
1M 4
1M 4
1M 4
1M 4
1M 4
1M 4
1M 4
Applications