MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 549

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

QUICC1 and QUICC2 exchange transparent frames and synchronize each other using the
RTS and CD pins. The CTS pin is not required since transmission may begin at any time.
Thus, the RTS signal is directly connected to the other QUICC’s CD pin. The RSYN option
in GSMR is not used, and transmission and reception from each QUICC are independent.
7.10.21.5 TRANSPARENT MEMORY MAP. When configured to operate in transparent
mode, the QUICC overlays the structure listed in Table 7-5 onto the protocol-specific area
of the SCC parameter RAM listed in Table 7-10.
(OUTPUT
(OUTPUT
(OUTPUT
NOTES:
IS CLKx
NOTES:
BRGOx
INPUT)
IS RXD
INPUT)
INPUT)
3. The transparent frame will contain a CRC if the TC bit is set in the Tx BD.
IS CD
2. The required GSMR configurations are: DIAG = 00, CTSS = 1, CTSP is a don't care, CDS = 1, CDP = 0, TTX = 1, and
1. CTS should be configured as always asserted in the port C parallel I/O or else connected to ground externally.
TXD
RTS
1. Each QUICC generates its own transmit clocks. If the transmit and receive clocks are the same, it is possible for one
TRX = 1. REVD and TCRC are application dependent.
clock the transmitter and receiver).
QUICC to generate transmit and receive clocks for the other QUICC (for example, CLKx on QUICC 2 could be used to
SCC Base + 30
SCC Base + 34
NOTE: The boldfaced items should be initialized by the user.
Address
Figure 7-64. Sending Transparent Frames Between QUICCs
QUICC 1
FIRST BIT OF FRAME DATA
Table 7-10. Transparent-Specific Parameters
BRGOx
CLKx
RXD
TXD
RTS
Freescale Semiconductor, Inc.
CD
For More Information On This Product,
CRC_P
CRC_C
Name
MC68360 USER’S MANUAL
Go to: www.freescale.com
Width
Long
Long
CRC Preset for Totally Transparent
CRC Constant for Totally Transparent Receiver
Serial Communication Controllers (SCCs)
LAST BIT OF FRAME DATA OR CRC
RXD
CD
CLKx
TXD
RTS
BRGOx
Description
L = 1 IN TX BD CAUSES
QUICC 2
NEGATION OF RTS
TERMINATES RECEPTION
CD LOST CONDITION
OF FRAME