MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 238

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
5.7.2.8 SINGLE OPERAND INSTRUCTIONS. The single operand instruction table indi-
cates the number of clock periods needed for the processor to perform the specified opera-
tion using the specified addressing mode. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
5.7.2.9 SHIFT/ROTATE INSTRUCTIONS. The shift/rotate instruction table indicates the
number of clock periods needed for the processor to perform the specified operation on the
given addressing mode. Footnotes indicate when to account for the appropriate EA times.
The number of bits shifted does not affect the execution time, unless noted. The total num-
5-96
ABCD
ABCD
SBCD
SBCD
ADDX
ADDX
SUBX
SUBX
CMPM (An)+, (Am)+
CLR
CLR
NEG
NEG
NEGX
NEGX
NOT
NOT
EXT
NBCD
NBCD
Scc
Scc
TAS
TAS
TST
X = There is one bus cycle for byte and word operands and two bus cycles for long-word
operands. For long-word bus cycles, add two clocks to the tail and to the number of
cycles.
Timing is calculated with the CPU32+ in 16-bit mode
Dn, Dm
Dn, Dm
Dn, Dm
Dn, Dm
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
CEA
FEA
FEA
FEA
FEA
CEA
CEA
FEA
(An), (Am)
(An), (Am)
(An), (Am)
(An), (Am)
Instruction
Instruction
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Head
Head
2
2
2
2
0
2
0
2
1
0
0
0
0
0
0
0
0
0
2
0
2
2
4
1
0
Tail
Tail
0
2
0
2
0
2
0
2
0
0
2
0
3
0
3
0
3
0
0
2
0
2
0
0
0
12(2/1/1)
12(2/1/1)
10(2/1/1)
10(2/1/1)
10(0/1/1)
4(0/1/0)
4(0/1/0)
2(0/1/0)
2(0/1/0)
8(2/1/0)
2(0/1/0)
4(0/1/X)
2(0/1/0)
5(0/1/X)
2(0/1/0)
5(0/1/X)
2(0/1/0)
5(0/1/X)
2(0/1/0)
4(0/1/0)
6(0/1/1)
4(0/1/0)
6(0/1/1)
6(0/1/0)
2(0/1/0)
Cycles
Cycles