MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 554

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
CR—CRC Error indication bits
OV—Overrun
CD—Carrier Detect Lost
Data Length
Rx Buffer Pointer
7.10.21.10 TRANSPARENT TRANSMIT BUFFER DESCRIPTOR (TX BD). Data is pre-
sented to the CP for transmission on an SCC channel by arranging it in buffers referenced
by the channel’s Tx BD table. The CP confirms transmission or indicates error conditions
using the BDs to inform the processor that the buffers have been serviced.
The status and control bits are prepared by the user before transmission and are set by the
CP after the buffer has been transmitted.
R—Ready
7-230
This frame contains a CRC error. The received CRC bytes are always written to the re-
ceive buffer.
A receiver overrun occurred during buffer reception.
The carrier detect signal was negated during buffer reception.
The data length is the number of octets that the CP has written into this BD’s data buffer.
It is written only once by the CP as the buffer is closed.
The receive buffer pointer, which always points to the first location of the associated data
buffer, must be divisible by 4 (unless the RFW bit in the GSMR is set to 8-bits wide, in
which case it may be even or odd). The buffer may reside in either internal or external
memory.
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
0 = The data buffer associated with this BD is not ready for transmission. The user is
1 = The data buffer, which has been prepared for transmission by the user, has not
free to manipulate this BD or its associated data buffer. The CP clears this bit after
the buffer has been transmitted or after an error condition is encountered.
been transmitted or is currently being transmitted. No fields of this BD may be writ-
ten by the user once this bit is set.
The actual amount of memory allocated for this buffer should be
greater than or equal to the contents of the maximum receive
buffer length register (MRBLR).
15
R
14
—
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
MC68360 USER’S MANUAL
11
L
Go to: www.freescale.com
TC
10
NOTE
CM
TX DATA BUFFER POINTER
9
DATA LENGTH
—
8
—
7
—
6
—
5
—
4
—
3
—
2
UN
1
CT
0