MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 226

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
5.7.1.3.1 Prefetch Controller. The instruction prefetch controller receives an initial request
from the microsequencer to initiate prefetching at a given address. Subsequent prefetches
are initiated by the prefetch controller whenever a pipeline stage is invalidated, either
through instruction completion or through use of extension words. Prefetch occurs as soon
as the bus is free of operand accesses previously requested by the microsequencer. Addi-
tional state information permits the controller to inhibit prefetch requests when a change in
instruction flow (e.g., a jump or branch instruction) is anticipated.
In a typical program, 10 to 25 percent of the instructions cause a change of flow. Each time
a change occurs, the instruction pipeline must be flushed and refilled from the new instruc-
tion stream. If instruction prefetches, rather than operand accesses, were given priority,
many instruction words would be flushed unused, and necessary operand cycles would be
delayed. To maximize available bus bandwidth, the CPU32+ will schedule a prefetch only
when the next instruction is not a change-of-flow instruction and when there is room in the
pipeline for the prefetch.
5.7.1.3.2 Write-Pending Buffer. The CPU32+ incorporates a single-operand write-pending
buffer. The buffer permits the microsequencer to continue execution after a request for a
write cycle is queued in the bus controller. The time needed for a write at the end of an
instruction can overlap the head cycle time for the following instruction, thus reducing overall
execution time. Interlocks prevent the microsequencer from overwriting the buffer.
5-84
MICROSEQUENCER AND CONTROL
CONTROL STORE
CONTROL LOGIC
ADDRESS
Figure 5-30. Block Diagram of Independent Resources
BUS
Freescale Semiconductor, Inc.
For More Information On This Product,
WRITE-PENDING
PROGRAM
COUNTER
SECTION
BUFFER
MC68360 USER’S MANUAL
Go to: www.freescale.com
EXECUTION UNIT
CONTROLLER
BUS CONTROL
MICROBUS
SIGNALS
STAGE
C
INSTRUCTION PIPELINE
SECTION
CONTROLLER
PREFETCH
DATA
STAGE
B
DATA
BUS