MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 699

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.15.4 Interrupt Vector Generation and Calculation
Pending unmasked CPM interrupts are presented to the CPU32+ core in order of priority.
The CPU32+ core responds to an interrupt request by initiating an interrupt acknowledge
cycle to receive a vector number, which allows the core to locate the interrupt’s service rou-
tine. For CPM interrupts, the CPIC passes an interrupt vector corresponding to the highest
priority, unmasked, pending interrupt. The CPM always generates a vector during an inter-
rupt acknowledge cycle at its interrupt level, regardless of whether the QUICC is in normal
mode or slave mode.
The three MSBs of the interrupt vector number are programmed by the user in the CIMR.
These three bits are concatenated with five bits generated by the CPIC to provide an 8-bit
vector number to the CPU32+ core. The CPIC’s encoding of the five low-order bits of the
interrupt vector is listed in Table 7-22.
Note that the interrupt vector table is the same as the CPM interrupt priority table except for
two differences. First, the lower five bits of the SCC vectors are fixed; they are not affected
by the SCC group or spread mode or the relative priority order of the SCCs. Second, an error
EVENT
MASK
BIT
BIT
SCCM
SCCE
Figure 7-100. Interrupt Request Masking
Freescale Semiconductor, Inc.
For More Information On This Product,
(13 EVENT BITS)
13 INPUT
MC68360 USER’S MANUAL
OR
Go to: www.freescale.com
MASK
BIT
CIMR
CIPR
(28 CIPR BITS)
28 INPUT
OR
CPM Interrupt Controller (CPIC)
REQUEST
TO THE IMB
AT THE
LEVEL
SPECIFIED
IN IRL2–IRL0
IN THE CICR.